This invention relates generally to complex application specific integrated circuits and more particularly to a distributed parallel processor architecture and design method which allows such complex integrated circuits to be easily designed.
Integrated circuit technology has advanced in the integration of gates from a small number (fewer that one hundred transistors) to a very large number (millions of transistors). As a result, it is possible to make integrated circuits (ICs) which perform increasingly complex functions and thereby to replace a large number of discrete components, with commensurate benefits in size, cost, and reliability. However, the complexity of the circuits and the large number of available transistors make designing ICs more difficult. Consequently, tools have been developed to help IC designers to design ICs in a more efficient manner. The aim of such tools is to make it easier for the designer to synthesize the target logic without the need to manipulate transistors or gates.
In general purpose processor architecture, primitive low-level instructions (such as add, multiply, compare, etc.) are implemented in hardware which can be sequenced into a programmed set of instructions to implement a complex function. Such an architecture is limited by the throughput achievable by the central processing unit (CPU) which must meet the peak throughput needs for a series of operations. Such a limitation often places a great demand on the hardware and results in inefficiencies in the utilization of designed hardware. In addition, power management of such a centrally controlled architecture is normally difficult.
In order to meet the design throughput goals with an efficient hardware implementation, designers often opt to use application specific integrated circuits design techniques at the cost of sacrificing the system design flexibility offered by post-synthesis programmability.
In general, two approaches have been developed to help IC designers--"standard cell" and "gate array" technologies. These technologies are discussed generally in U.S. Pat. Nos. 5,119,314 (Hotta et al.), 5,173,864 (Watanabe et al.), 5,197,016 (Sugimoto et al.), and 5,283,753 (Schucker et al.). In the standard cell approach, commonly used logic blocks are carefully designed and stored in a cell library. Designers can retrieve and interconnect appropriate logic blocks so as to provide desired functions. Typically, these blocks are primitive logic structures, such as NAND or NOR gates, or other simple logic blocks, such as an adder or multiplier. Logic blocks can be interconnected by routing conductors between the appropriate input/output terminals of the blocks.
Gate array technology involves the fabrication of a large number of base wafers containing identical integrated circuit elements (gates) up to but not including the first level of conductive interconnect. IC designers "customize" the gate array by specifying only the conductive patterns used to interconnect the pre-fabricated gates.
One of the problems with both these approaches is that it is difficult to use them to design ICs which perform complicated functions. This is because the standard cells and gate arrays are primitive or simple logic blocks for all types of applications. Consequently, it takes a lot of time, skill, and effort to integrate these basic building blocks into useful application specific integrated circuits. In addition, the layout and timing constraints and the design effort required to interconnect these logic blocks normally limit the designers freedom and increase the design time.
As an example, circuits used for communication applications typically perform complex signal processing operations. Examples of such circuits are finite impulse response filters, infinite impulse response filters, demodulators, and correlators. These circuits incorporate complicated mathematical algorithms which could be understood and designed only by extremely skilled engineers. Consequently, it is very tedious to implement these circuits using the primitive building blocks available with standard cell and gate array technologies.
Some of the layout constraints associated with the design of complex integrated circuits using standard cells and gate array design methods are dealt with in Schucker et al. The block architectured integrated circuit design approach described therein allows for re-use of earlier developed logic blocks, but it does not address the complexity of interconnecting the various logic blocks. In addition, the described integrated circuit design approach does not provide for power management, which is an important factor for complex ICs incorporating a large number of gates.
Some electronic system manufacturers take a completely different strategy to solve the aforementioned problem. Instead of relying on custom designed ICs, they use general purpose ICs, such as microcontrollers and digital signal processors. These ICs are able to execute a large number of instructions per second. Typically, software is used to customize the function of these ICs.
One of the problems of using these general purpose ICs is that they cannot attain throughput comparable to that of an application specific IC. In many applications where processing speed is a crucial factor, such as high speed communication systems, the performance of general purpose ICs is not acceptable. Further, the use of software does not change the requirement that extremely skilled engineers are needed to implement the complicated processing algorithm.
Sugimoto et al. discloses a computer-aided system and method for designing application specific integrated circuits incorporating a general purpose processor and a plurality of logic blocks connected together on a multiplicity of data, address, and control busses. This design approach suffers from several drawbacks. First, it lacks the ability to perform post-synthesis programming for the logic blocks synthesized by the integrated silicon-software compiler into hardware blocks; namely the primitive support functions, such as comparators, adders, multipliers, and counters, which are incorporated to enhance the system throughput. In addition, the processing needs of complex algorithms are still implemented in software and thus require a skilled designer for a complex system. In addition, the integrated circuit design approach described in Sugimoto et al. does not incorporate provision for power management.
Hence, a need exists for a block architectured application specific integrated circuit and design method that allows effective encapsulation of complex application specific processing into function blocks which can be re-used from one design to another, but can be post-synthesis programmed to meet the evolution enhancement and upgrade needs of the specific application with power efficient integrated circuit design.